1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a technology for reducing power consumption while maintaining high speed operation.
2. Description of the Related Art
In general, semiconductor memories have a page operation function in which data that is read simultaneously from a plurality of memory cells connected to a word line is output in succession. The page operation function can accelerate operations subsequent to the activation of the memory block, with an improvement in data transfer rate.
For yet improved data transfer rate, there has been recently developed a semiconductor memory which has a high speed page operation function in which a plurality of bits of data is simultaneously read and retained into a register or the like in response to a single read command.
FIG. 1 shows an overview of a semiconductor memory having the high speed page operation function of this type.
The semiconductor memory has four memory blocks BLK1–BLK4. The memory blocks BLK1–BLK4 have column decoders CDEC1–CDEC4 for selecting column selecting lines CL1–CL4 in accordance with a column address, precharging units PRE1–PRE4 having precharging circuits for bit lines BL and /BL, sense amplifier units SA1–SA4 having sense amplifiers SA, memory cell arrays ARY1–ARY4 having memory cells MC, amplifier units AMP1–AMP4 having read amplifiers and write amplifiers, and latch units LTCH1–LTCH4 having latch circuits. Word lines WL are laid common to the four memory blocks BLK1–BLK4.
In this semiconductor memory, all the memory blocks BLK1–BLK4 are activated in accordance with a read command. A predetermined word line WL is selected in accordance with a row address which is supplied along with the read command. Next, the sense amplifiers SA of the sense amplifier units SA1–SA4 are activated to amplify data that is read from the memory cells MC to the bit lines BL and /BL. That is, the four memory blocks BLK1–BLK4 are all activated in response to the read command.
Then, the column selecting lines CL1–CL4 are simultaneously selected in accordance with a column address, turning on four column switches CSW. The data amplified by the sense amplifiers SA is transmitted to local data bus lines LDB1–LDB4 through the column switches CSW, respectively. The parallel read data is transmitted from the local data bus lines LDB1–LDB4 to global data bus lines GDB1–GDB4, and further amplified by the read amplifiers of the amplifier units AMP1–AMP4.
The parallel data amplified by the read amplifiers is converted into serial data by a parallel/serial conversion circuit, and output to a data terminal in succession. The number of times the data is output to the data terminal in response to a single read command is referred to as burst length. In this example, the burst length is “4”. Each time the semiconductor memory receives a read command, it repeats the above-described operation to perform a read operation.
FIG. 2 shows an overview of another semiconductor memory having the high speed page operation function. The same elements as in FIG. 1 are designated by identical numbers.
The semiconductor memory has four memory blocks BLK1–BLK4. Word lines WL are laid by each of the four memory blocks BLK. Then, in accordance with a row address supplied along with a read command, any one of the memory blocks BLK1–BLK4 is selected (in this example, BLK1) and a word line WL in the selected memory block BLK1 is selected. Next, the sense amplifiers SA of the sense amplifier unit SA1 in the memory block BLK1 are activated to amplify data that is read from the memory cells MC to the bit lines BL and /BL. That is, in this semiconductor memory, any one of the four memory blocks BLK1–BLK4 is activated in response to the read command.
Next, in the selected memory block BLK1, the column selecting lines CL1–CL4 are selected in accordance with a column address so that four column switches CSW are turned on simultaneously. The data amplified by the sense amplifiers SA is transmitted to local data bus lines LDB1–LDB4 in the memory block BLK1 through the column switches CSW, respectively. The parallel read data is transmitted from the local data bus lines LDB1–LDB4 to global data bus lines GDB1–GDB4 in the memory block BLK1, and further amplified by the read amplifiers of the amplifier unit AMP1.
As in FIG. 1, the parallel data amplified by the read amplifiers is converted into serial data by a parallel/serial conversion circuit, and output to a data terminal in succession. In this example, the burst length is also “4”. Each time the semiconductor memory receives a read command, it repeats the above-described operation to perform a read operation.
In the semiconductor memory shown in FIG. 1 a problem arises that activation of all the memory blocks BLK during a read operation increases power consumption.
In the semiconductor memory shown in FIG. 2, a single memory block BLK is activated in a read operation. Nevertheless, the global data bus lines GDB1–GDB4 must be laid in each of the memory blocks BLK. Aside from those shown in the diagram, the memory blocks BLK are also provided with power supply lines and the like. Hence, if the wiring regions of the global data bus lines GDB1–GDB4 cannot be secured inside the memory blocks BLK at the stage of layout design, it is necessary to secure the wiring regions of the global data bus lines GDB1–GDB4 by such means as reducing the wiring width of the power supply lines. In this case, power supply noise is likely to occur due to increases in the power supply resistance. When the wiring width of the power supply lines is unchanged, the individual memory blocks BLK must be enlarged in conformity to the wiring regions of the global data bus lines GDB1–GDB4. This results in increasing the semiconductor memory in chip size.